There are many different types of semiconductor memories. Some semiconductor memories, commonly known as read-only memories (ROMs), have data stored in them once, and then the data cannot be changed, but can be read any number of times. Some types of semiconductor memory, including ROMs, are non-volatile and will hold stored data even in the absence of power. Although the data in a true ROM cannot be changed once it is stored, many types of non-volatile memory allow the data stored within them to be changed, although in some cases, there are limitations on how many times data can be changed or limitations on how the data is changed. Examples of non-volatile semiconductor memory include, but are not limited to, electrically erasable programmable read-only memory (EEPROM), NAND flash memory, NOR flash memory, phase-change memory (PCM), and ferroelectric memory (FeRAM).
Other types of memory are volatile and will lose the data stored within them if power is lost. Examples of volatile memory include, but are not limited to, registers, latches, static random access memory (SRAM) with multiple transistors per memory cell, and dynamic random access memory (DRAM) with a single transistor and a capacitor for each memory cell. Typically, a memory cell within a DRAM stores an amount of charge on the capacitor within the memory cell to indicate whether a binary ‘0’ or a binary ‘1’ is stored in the memory cell. In most DRAM architectures, the amount of charge stored in the capacitor may slowly change over time, which if left unchecked, would cause the data stored in the cell to change. This potential cause of memory corruption can be avoided by refreshing the cell on a regular basis to reset the amount of stored charge to the correct amount to preserve a correct value for the stored data. The time between refreshes must be rapid enough to preserve the cell's data value, to not allow transistor leakage to change the value before the next refresh of the cell is completed.
Some DRAMs, including double-data-rate (e.g. DDR3 and DDR4) and low-power DDR (LPDDR4) devices largely conforming to the joint electron device engineering council (JEDEC) standards for such devices, have an internal organization that is partitioned into regions commonly known as banks, pages or a subset of the memory. Pages are further divided into rows and columns, where a single memory cell is identified as being in one particular row and one particular column within the page. To access the data contained within a particular page, row, and column, address decoders specify the page and row to be activated, and then one or more columns are accessed with the activated page and row.
While semiconductor memory devices have been improved over the last several decades to reliably store large amounts of data, there are many different ways that data stored in a semiconductor memory can be corrupted. Many types of manufacturing defects can cause the reliability of memory to be compromised; alpha particles can impact a cell and cause errors; and, in some memories, certain data patterns can cause errors, to name a few. Some memory devices have a property where repeated activation of one region, such as a memory row, can corrupt the data stored in a nearby region, such as an adjacent row. This property is sometimes referred to as “row hammering.”